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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPS54340B-Q1 slvsdx5 ? february 2017 TPS54340B-Q1 4.5-v to 42-v input, 3.5-a, step-down dc-dc converter with eco-mode ? 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ambient operating temperature range ? device hbm esd classification level h1c ? device cdm esd classification level c3b ? high efficiency at light loads with pulse skipping eco-mode ? ? 92-m high-side mosfet ? 146- a operating quiescent current and 2- a shutdown current ? 100-khz to 2.5-mhz adjustable switching frequency ? synchronizes to external clock ? low dropout at light loads with integrated boot recharge fet ? adjustable uvlo voltage and hysteresis ? 0.8 v 1% internal voltage reference ? 8-pin hsop with powerpad ? package ? ? 40 c to 150 c t j operating range ? supported by webench ? software tool 2 applications ? vehicle accessories: gps (see slva412 ), entertainment, adas, ecall ? usb dedicated charging ports and battery chargers (see slva464 ) ? industrial automation and motor control ? 12-v and 24-v industrial, automotive, and communications power systems space 3 description the TPS54340B-Q1 device is a 42-v, 3.5-a, step- down regulator with an integrated high-side mosfet. the device survives load-dump pulses up to 45 v per iso 7637. current-mode control provides simple external compensation and flexible component selection. a low-ripple pulse-skip mode reduces the no-load supply current to 146 a. shutdown supply current is reduced to 1 a when the enable pin is pulled low. undervoltage lockout is internally set at 4.3 v but can be increased using an external resistor divider at the enable pin. the output voltage start-up ramp is internally controlled to provide a controlled start-up and eliminate overshoot. a wide adjustable frequency range allows for optimization of either efficiency or external component size. frequency foldback and thermal shutdown protects internal and external components during an overload condition. the TPS54340B-Q1 device is available in an 8-pin thermally-enhanced hsop powerpad package. device information (1) part number package body size (nom) TPS54340B-Q1 hsop (8) 4.89 mm 3.90 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic efficiency vs load current 0 10 20 30 40 50 60 70 80 100 0 0.5 1.0 1.5 2.0 i - output current - a o efficiency - % 2.5 3.0 90 3.5 v = 5v out v = 3.3v out v = 12v sw = 600 khz in f sw vin gnd boot fb comp TPS54340B-Q1 en rt/clk v in v out r1r3 copyright ? 2016, texas instruments incorporated productfolder ordernow technical documents tools & software referencedesign support &community
2 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ..................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 rt/clk timing requirements .................................. 5 6.7 switching characteristics .......................................... 6 6.8 typical characteristics .............................................. 7 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagram ....................................... 12 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 22 8 application and implementation ........................ 23 8.1 application information ............................................ 23 8.2 typical applications ................................................ 23 9 power supply recommendations ...................... 35 10 layout ................................................................... 35 10.1 layout guidelines ................................................. 35 10.2 layout example .................................................... 36 10.3 estimated circuit area .......................................... 36 11 device and documentation support ................. 37 11.1 device support ...................................................... 37 11.2 documentation support ........................................ 37 11.3 community resources .......................................... 37 11.4 trademarks ........................................................... 37 11.5 electrostatic discharge caution ............................ 37 11.6 glossary ................................................................ 37 12 mechanical, packaging, and orderable information ........................................................... 37 4 revision history date revision notes february 2017 * initial release.
3 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions dda package 8-pin hsop top view pin functions pin i/o description name no. boot 1 o a bootstrap capacitor is required between boot and sw. if the voltage on this capacitor is below the minimum required to operate the high-side mosfet, the output switches off until the capacitor is refreshed. comp 6 o error amplifier output and input to the output switch current (pwm) comparator. connect frequency compensation components to this pin. en 3 i enable pin, with internal pullup current source. pull below 1.2 v to disable. float to enable. adjust the input undervoltage lockout with two resistors. see the enable and adjusting undervoltage lockout section. fb 5 i inverting input of the transconductance (gm) error amplifier. gnd 7 ? ground rt/clk 4 i resistor timing and external clock. an internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. if the pin is pulled above the pll upper threshold, a mode change occurs and the pin becomes a synchronization input. the internal amplifier is disabled and the pin is a high impedance clock input to the internal pll. if clocking edges stop, the internal amplifier is reenabled and the operating mode returns to resistor frequency programming. sw 8 i the source of the internal high-side power mosfet and switching node of the converter. thermal pad 9 ? gnd pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation. vin 2 i input supply voltage with 4.5-v to 42-v operating range. gnd 7 comp 6 fb 5 sw 8 23 4 1 vin en rt/clk boot powerpad 9
4 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input voltage vin ? 0.3 45 v en ? 0.3 8.4 boot 53 fb ? 0.3 3 comp ? 0.3 3 rt/clk ? 0.3 3.6 output voltage boot-sw 8 v sw ? 0.6 45 sw, 10-ns transient ? 2 45 operating junction temperature ? 40 150 c storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged device model (cdm), per jedec specification jesd22- c101 (2) 500 (1) see equation 1 in the feature description section. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v in supply input voltage (1) v o + v do 42 v v o output voltage 0.8 58.8 v i o output current 0 3.5 a t j junction temperature ? 40 150 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . (2) power rating at a specific ambient temperature ta should be determined with a junction temperature of 150 c. this is the point where distortion starts to substantially increase. see power dissipation estimate in application section of this data sheet for more information. 6.4 thermal information thermal metric (1) (2) TPS54340B-Q1 unit dda (hsop) 8 pins r ja junction-to-ambient thermal resistance (standard board) 42 c/w r jc(top) junction-to-case(top) thermal resistance 45.8 c/w r jb junction-to-board thermal resistance 23.4 c/w jt junction-to-top characterization parameter 5.9 c/w jb junction-to-board characterization parameter 23.4 c/w r jc(bot) junction-to-case(bottom) thermal resistance 3.6 c/w
5 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) open loop current limit measured directly at the sw pin and is independent of the inductor value and slope compensation. 6.5 electrical characteristics t j = ? 40 c to 150 c, vin = 4.5 v to 42 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin pin) operating input voltage 4.5 42 v internal undervoltage lockout threshold rising 4.1 4.3 4.48 v internal undervoltage lockout threshold hysteresis 325 mv shutdown supply current en = 0 v, 25 c, 4.5 v vin 42 v 2.25 4.5 a operating: nonswitching supply current fb = 0.9 v, t a = 25 c 146 175 enable and uvlo (en pin) enable threshold voltage no voltage hysteresis, rising and falling 1.1 1.2 1.3 v input current enable threshold 50 mv ? 4.6 a enable threshold ? 50 mv ? 0.58 ? 1.2 -1.8 hysteresis current ? 2.2 ? 3.4 -4.5 a enable to comp active vin = 12 v , t a = 25 c 346 s internal soft-start time soft-start time f sw = 500 khz, 10% to 90% 2.1 ms soft-start time f sw = 2.5 mhz, 10% to 90% 0.42 ms voltage reference voltage reference 0.792 0.8 0.808 v high-side mosfet on-resistance vin = 12 v, boot-sw = 6 v 92 190 m error amplifier input current 50 na error amplifier transconductance (g m ) ? 2 a < i comp < 2 a, v comp = 1 v 350 s error amplifier transconductance (g m ) during soft-start ? 2 a < i comp < 2 a, v comp = 1 v, v fb = 0.4 v 77 s error amplifier dc gain v fb = 0.8 v 10,000 v/v min unity gain bandwidth 2500 khz error amplifier source and sink v (comp) = 1 v, 100-mv overdrive 30 a comp to sw current transconductance 12 a/v current limit current limit threshold all vin and temperatures, open loop (1) 4.5 5.5 6.8 a all temperatures, vin = 12 v, open loop (1) 4.5 5.5 6.25 vin = 12 v, t a = 25 c, open loop (1) 5.2 5.5 5.85 current limit threshold delay 60 ns thermal shutdown thermal shutdown 176 c thermal shutdown hysteresis 12 c timing resistor and external clock (rt/clk pin) rt/clk high threshold 1.55 2 v rt/clk low threshold 0.5 1.2 v 6.6 rt/clk timing requirements min nom max unit minimum clk input pulse width 15 ns
6 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.7 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit timing resistor and external clock (rt/clk pin) switching frequency range using rt mode 100 2500 khz ? sw switching frequency r t = 200 k 450 500 550 khz switching frequency range using clk mode 160 2300 khz rt/clk falling edge to sw rising edge delay measured at 500 khz with rt resistor in series 55 ns pll lock in time measured at 500 khz 78 s
7 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.8 typical characteristics figure 1. on resistance vs junction temperature figure 2. voltage reference vs junction temperature figure 3. switch current limit vs junction temperature figure 4. high-side switch current limit vs input voltage figure 5. switching frequency vs junction temperature figure 6. switching frequency vs rt/clk resistance low-frequency range 0 50 100 150 200 250 300 350 400 450 500 200 300 400 500 600 700 800 900 1000 rt/clk ? resistance (k w ) ? sw ? switching frequency (khz) ? sw (khz) = 92417 r t (k w ) - 0.991 r t (k w ) = 101756 f sw (khz) - 1.008 g006 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) high-side switch current (a) v in = 12 v g003 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5 0 10 20 30 40 50 60 v in ? input voltage (v) high-side switch current (a) t j = ?40c t j = 25c t j = 150c g004 0 0.05 0.1 0.15 0.2 0.25 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) r ds ( on ) ? on-state resistance ( w ) boot-sw = 3 vboot-sw = 6 v g001 0.784 0.789 0.794 0.799 0.804 0.809 0.814 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) v fb ? voltage reference (v) v in = 12 v g002 450 460 470 480 490 500 510 520 530 540 550 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) ? sw ? switching frequency (khz) rt = 200 k w , v in = 12 v g005
8 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 7. switching frequency vs rt/clk resistance high-frequency range figure 8. ea transconductance vs junction temperature figure 9. ea transconductance during soft start vs junction temperature figure 10. en pin voltage vs junction temperature figure 11. en pin current vs junction temperature figure 12. en pin current vs junction temperature ?2.5 ?2.3 ?2.1 ?1.9 ?1.7 ?1.5 ?1.3 ?1.1 ?0.9 ?0.7 ?0.5 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) i en (a) v in = 5 v, i en = threshold+50mv g011 ?5 ?4.9 ?4.8 ?4.7 ?4.6 ?4.5 ?4.4 ?4.3 ?4.2 ?4.1 ?4 ?50 ?25 0 25 50 75 100 125 150 tj ? junction temperature (c) i en (a) v in = 12 v, i en = threshold+50mv g012 20 30 40 50 60 70 80 90 100 110 120 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) gm (ua/v) v in = 12 v g009 1.15 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.3 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) en ? threshold (v) v in = 12 v g010 0 500 1000 1500 2000 2500 0 50 100 150 200 rt/clk ? resistance (k w ) ? sw ? switching frequency (khz) g007 200 250 300 350 400 450 500 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) gm (db) v in = 12 v g008
9 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 13. en pin current hysteresis vs junction temperature figure 14. switching frequency vs fb figure 15. shutdown supply current vs junction temperature figure 16. shutdown supply current vs input voltage (v in ) figure 17. v in supply current vs junction temperature figure 18. v in supply current vs input voltage 70 90 110 130 150 170 190 210 0 v in ? input voltage (v) v in ? supply current (a) g018 5 15 20 25 30 40 35 45 10 70 90 110 130 150 170 190 210 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) v in ? supply current (db) v in = 12 v g016 0 0.5 1 1.5 2 2.5 3 0 v in ? input voltage (v) shutdown supply current (a) g016 t j = 25c 5 15 20 25 30 40 35 45 10 0 0.5 1 1.5 2 2.5 3 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) shutdown supply current (a) v in = 12 v g014 ?4.5 ?4.3 ?4.1 ?3.9 ?3.7 ?3.5 ?3.3 ?3.1 ?2.9 ?2.7 ?2.5 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) en pin current hysteresis (a) v in = 12 v g112 0 25 50 75 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v fb (v) % of nominal switching frequency v fb falling v fb rising g013
10 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 19. boot-sw uvlo vs junction temperature figure 20. input voltage uvlo vs junction temperature figure 21. soft-start time vs switching frequency 1 2 3 4 5 6 7 9 10 100 300 500 700 900 switching frequency (khz) soft-start time (ms) g021 11001300 1500 17001900 2100 2300 2500 0 8 t = 25 c j o v = 12v, in 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 ?50 ?25 0 25 50 75 100 125 150 t j ? junction temperature (c) v in ? (boot?sw) (db) boot-sw uvlo fallingboot-sw uvlo rising g018 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 ?50 ?25 0 25 50 75 100 125 150 tj ? junction temperature (c) input voltage (v) uvlo start switchinguvlo stop switching g019
11 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the TPS54340B-Q1 device is a 42-v, 3.5-a, step-down (buck) regulator with an integrated high-side n-channel mosfet. the device implements constant-frequency current-mode control, which reduces output capacitance and simplifies external frequency compensation. the wide switching-frequency range of 100 khz to 2500 khz allows for either efficiency or size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground connected to the rt/clk pin. the device has an internal phase- locked loop (pll) connected to the rt/clk pin that synchronizes the power switch turnon to a falling edge of an external clock signal. the TPS54340B-Q1 device has a default input start-up voltage of approximately 4.3 v. the en pin adjusts the input voltage undervoltage lockout (uvlo) threshold with two external resistors. an internal pullup current source enables operation when the en pin is floating. the operating current is 146 a under no load condition (not switching). when the device is disabled, the supply current is 1 a. the integrated 92-m high-side mosfet supports high-efficiency power-supply designs capable of delivering 3.5 a of continuous current to a load. the gate-drive bias voltage for the integrated high-side mosfet is supplied by a bootstrap capacitor connected from the boot to sw pins. the TPS54340B-Q1 device reduces the external component count by integrating the bootstrap recharge diode. the boot pin capacitor voltage is monitored by a uvlo circuit which turns off the high-side mosfet when the boot to sw voltage falls below a preset threshold. an automatic boot capacitor recharge circuit allows the TPS54340B-Q1 device to operate at high duty cycles approaching 100%. therefore, the maximum output voltage is near the minimum input supply voltage of the application. the minimum output voltage is the internal 0.8-v feedback reference. output-overvoltage transients are minimized by an overvoltage protection (ovp) comparator. when the ovp comparator is activated, the high-side mosfet turns off and remains off until the output voltage is less than 106% of the desired output voltage. the TPS54340B-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-rush current and output voltage overshoot. output overload conditions reset the soft-start timer. when the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. a frequency-foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor current.
12 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.2 functional block diagram 7.3 feature description 7.3.1 fixed-frequency pwm control the TPS54340B-Q1 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. the output voltage is compared through external resistors connected to the fb pin to an internal voltage reference by an error amplifier. an internal oscillator initiates the turnon of the high-side power switch. the error amplifier output at the comp pin controls the high-side power-switch current. when the high-side mosfet switch current reaches the threshold level set by the comp voltage, the power switch turns off. the comp pin voltage increases and decreases as the output current increases and decreases. the device implements current limiting by clamping the comp-pin voltage to a maximum level. the pulse skipping eco-mode is implemented with a minimum voltage clamp on the comp pin. 7.3.2 slope compensation output current the TPS54340B-Q1 device adds a compensating ramp to the mosfet switch-current sense signal. this slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range. error amplifier boot charge boot uvlo uvlo current sense oscillator with pll frequency foldback logic slope compensation pwm comparator minimum clamp pulse skip maximum clamp voltage reference reference dac for soft - start fb comp rt/ clk sw boot vin gnd thermal shutdown en enable comparator shutdown logic shutdown enable threshold 6 8/8/ 2012 a 0192789 logic shutdown powerpad shutdown ov copyright ? 2017, texas instruments incorporated
13 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.3 pulse skip eco-mode ? the TPS54340B-Q1 device operates in a pulse skipping eco-mode at light-load currents to improve efficiency by reducing switching and gate-drive losses. if the output voltage is within regulation and the peak-switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters eco-mode. the pulse-skipping current threshold is the peak switch-current level corresponding to a nominal comp voltage of 600 mv. when in eco-mode, the comp pin voltage is clamped at 600 mv and the high-side mosfet is inhibited. because the device is not switching, the output voltage begins to decay. the voltage control loop responds to the falling output voltage by increasing the comp pin voltage. the high-side mosfet enables and switching resumes when the error amplifier lifts comp above the pulse skipping threshold. the output voltage recovers to the regulated value, and comp eventually falls below the eco-mode pulse-skipping threshold at which time the device again enters eco-mode. the internal pll remains operational when in eco-mode. when operating at light-load currents in eco-mode, the switching transitions occur synchronously with the external clock signal. during eco-mode operation, the TPS54340B-Q1 device senses and controls peak switch current, not the average load current. therefore the load current at which the device enters eco-mode is dependent on the output inductor value. the circuit in figure 33 enters eco-mode at about 31.4-ma output current. as the load current approaches zero, the device enters a pulse-skip mode during which it draws only 146- a input quiescent current. 7.3.4 low dropout operation and bootstrap voltage (boot) the TPS54340B-Q1 device provides an integrated-bootstrap voltage regulator. a small capacitor between the boot and sw pins provides the gate drive voltage for the high-side mosfet. the boot capacitor refreshes when the high-side mosfet is off and the external low-side diode conducts. the recommended value of the boot capacitor is 0.1 f. for stable performance over temperature and voltage, ti recommends a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher. when operating with a low-voltage difference from input to output, the high-side mosfet of the TPS54340B-Q1 device operates at 100% duty cycle as long as the boot to sw pin voltage is greater than 2.1 v. when the voltage from boot to sw drops to less than 2.1 v, the high-side mosfet turns off and an integrated low-side mosfet pulls sw low to recharge the boot capacitor. to reduce the losses of the small low-side mosfet at high-output voltages, it is disabled at 24-v output and reenabled when the output reaches 21.5 v. because the gate drive current sourced from the boot capacitor is small, the high-side mosfet can remain on for many switching cycles before the mosfet is turned off to refresh the capacitor. thus, the effective duty cycle of the switching regulator can be high, approaching 100%. the effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power mosfet, the inductor resistance, the low- side diode voltage, and the printed-circuit-board resistance. calculates the minimum input voltage required to regulate the output voltage and ensure proper operation of the device. this calculation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application. where ? v f = schottky diode forward voltage ? r dc = dc resistance of inductor plus pcb ? r ds(on) = high-side mosfet resistance ? d = effective duty cycle of 99%. (1) during high-duty-cycle (low-dropout) conditions, the inductor-current ripple increases when the boot capacitor recharges which results in an increase in output voltage ripple. increased ripple occurs when the off time required to recharge the boot capacitor is longer than the high-side off time associated with cycle-by-cycle pwm control. at heavy loads, the minimum input voltage must be increased to ensure a monotonic start-up. equation 2 calculates the minimum input voltage for this condition. ( ) ( ) out f dc out in ds out f v v r i v min r on i v d + + = + -
14 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) v o max = dmax (v vin min ? i o max r ds(on) + v f ) ? v f ? i o max r dc where ? dmax 0.9 ? r ds(on) = 1 / ( ? 0.3 vb2sw 2 + 3.577 vb2sw ? 4.246) ? vb2sw = vboot + v f ? vboot = (1.41 v vin ? 0.554 ? v f ? sw 10 ? 6 ? 1.847 10 3 ib2sw) / (1.41 + ? sw 10 -6 ) ? ib2sw = 100 10 ? 6 a (2) 7.3.5 error amplifier the TPS54340B-Q1 voltage regulation loop is controlled by a transconductance error amplifier. the error amplifier compares the fb pin voltage to the lower of the internal soft-start voltage or the internal 0.8-v voltage reference. the transconductance (gm) of the error amplifier is 350 a/v during normal operation. during soft- start operation, the transconductance is reduced to 78 a/v and the error amplifier is referenced to the internal soft-start voltage. the frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output comp pin and gnd pin. 7.3.6 adjusting the output voltage the internal voltage reference produces a precise 0.8 v 1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. the output voltage is set by a resistor divider from the output node to the fb pin. ti recommends using divider resistors with a 1% tolerance or better. select the low-side resistor r ls for the desired divider current, and use equation 3 to calculate r hs . to improve efficiency at light loads, consider using larger value resistors. however, if the values are too high, the regulator is more susceptible to noise and voltage errors from the fb input current may become noticeable. (3) 7.3.7 enable and adjusting undervoltage lockout the TPS54340B-Q1 device is enabled when the vin-pin voltage rises above 4.3 v and the en-pin voltage exceeds the enable threshold of 1.2 v. the TPS54340B-Q1 device is disabled when the vin pin voltage falls to less than 4 v, or when the en pin voltage is less than 1.2 v. the en pin has an internal pullup current source, i1, of 1.2 a that enables operation of the TPS54340B-Q1 device when the en pin floats. if an application requires a higher undervoltage lockout (uvlo) threshold, use the circuit shown in figure 22 to adjust the input voltage uvlo with two external resistors. when the en pin voltage exceeds 1.2 v, an additional 3.4 a of hysteresis current, ihys, is sourced out of the en pin. when the en pin is pulled to less than 1.2 v, the 3.4 a ihys current is removed. this additional current facilitates adjustable input voltage uvlo hysteresis. use equation 4 to calculate r uvlo1 for the desired uvlo hysteresis voltage. use equation 5 to calculate r uvlo2 for the desired vin start voltage. in applications designed to start at relatively low input voltages (for example 4.5 v) and withstand high input voltages (for example 40 v), the en pin can experience a voltage greater than the absolute maximum voltage of 8.4 v during the high-input voltage condition. ti recommends using a zener diode to clamp the pin voltage below the absolute maximum rating. hs ls vout 0.8v r = r 0.8 v - ? ? ? ?
15 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 22. adjustable undervoltage lockout (uvlo) figure 23. internal en clamp (4) (5) 7.3.8 internal soft-start the tps54340-q1 device has an internal digital soft-start that ramps the reference voltage from 0 v to the final value in 1024 switching cycles. the internal soft-start time (10% to 90%) is calculated using equation 6 (6) if the en pin is pulled below the stop threshold of 1.2 v, switching stops and the internal soft start resets. the soft start also resets in thermal shutdown. 7.3.9 constant switching frequency and timing resistor (rt/clk) pin) the switching frequency of the TPS54340B-Q1 device is adjustable over a wide range from 100 khz to 2500 khz by placing a resistor between the rt/clk pin and gnd pin. the rt/clk pin voltage is typically 0.5 v and must have a resistor to ground to set the switching frequency. to determine the timing resistance for a given switching frequency, use equation 7 or equation 8 or the curves in figure 5 and figure 6 . to reduce the solution size one typically sets the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage, and minimum controllable on time must be considered. the minimum-controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high input-to-output step-down ratios. the maximum switching frequency is also limited by the frequency-foldback circuit. a more detailed discussion of the maximum switching frequency is provided in accurate current limit operation and maximum switchign frequency . (7) (8) 0.991 92417 sw (khz) = rt (k ) w f t 1.008 101756 r (k ) = sw (khz) w f f = ss sw 1024 t (ms) (khz) = - + ena uvlo2 start ena 1 uvlo1 v r v v i r - = start stop uvlo1 hys v v r i TPS54340B-Q1 i vin r uvlo1 r uvlo2 en optional v en ihys 1 copyright ? 2016, texas instruments incorporated vin r uvlo1 r uvlo2 en node 5.8 v 10 k w copyright ? 2016, texas instruments incorporated
16 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.10 accurate current limit operation and maximum switchign frequency the TPS54340B-Q1 device implements peak-current-mode control in which the comp-pin voltage controls the peak current of the high-side mosfet. a signal proportional to the high-side switch current and the comp pin voltage are compared each cycle. when the peak switch current intersects the comp control voltage, the high- side switch turns off. during overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the comp pin high. the error amplifier output is clamped internally at a level which sets the peak switch-current limit. the TPS54340B-Q1 device provides an accurate current limit threshold with a typical current limit delay of 60 ns. with smaller inductor values, the delay results in a higher peak inductor current. the relationship between the inductor value and the peak inductor current is shown in figure 24 . figure 24. current limit delay to protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340B-Q1 device implements a frequency foldback. the oscillator frequency is divided by 1, 2, 4, and 8 as the fb pin voltage falls from 0.8 v to 0 v. the TPS54340B-Q1 device uses a digital-frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. during short circuit events, the inductor current exceeds the peak current limit because of the high input voltage and the minimum-controllable on time. when the shorted load forces the output voltage low, the inductor current decreases slowly during the switch-off time. the frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down. with a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is controlled by frequency-foldback protection. equation 10 calculates the maximum switching frequency at which the inductor current remains under control when v out is forced to v out(sc) . the selected operating frequency must not exceed the calculated value. equation 9 calculates the maximum switching-frequency limitation set by the minimum-controllable on time and the input-to-output step-down ratio. setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage. (9) ( ) ( ) o dc out d sw max skip on in o d ds on i r v v 1 t v i r v f ? ? + + ? = ? - + ? t on t cldelay inductor current (a) clpeak peak inductor current open loop current limit clpeak = v /l x t in cldelay
17 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) where ? i o is the output current ? i cl is the current limit ? r dc is the inductor resistance ? v in is the maximum input voltage ? v out is the output voltage ? v out(sc) is the output voltage during short ? v d is the diode voltage drop ? r ds(on) is the switch on-resistance ? t on is the controllable on-time ? f div is the frequency divide equals (1, 2, 4, or 8) (10) 7.3.11 synchronization to rt/clk pin the rt/clk pin receives a frequency-synchronization signal from an external system clock. to implement this synchronization feature connect a square wave to the rt/clk pin through either circuit network shown in figure 25 . the square wave applied to the rt/clk pin must switch lower than 0.5 v but higher than 1.7 v, and it must have a pulse-width greater than 15 ns. the synchronization frequency range is 160 khz to 2300 khz. the rising edge of the sw synchronizes to the falling edge of rt/clk pin signal. the external synchronization circuit must be designed so that the default-frequency set-resistor is connected from the rt/clk pin to ground when the synchronization signal is off. when using a low-impedance signal source, the frequency set resistor is connected in parallel with an ac-coupling capacitor to a termination resistor (for example 50 ) as shown in figure 25 . the two resistors in series provide the default-frequency setting resistance when the signal source is turned off. the sum of the resistance must set the switching frequency close to the external clk frequency. ti recommends to ac-couple the synchronization signal through a 10-pf ceramic capacitor to rt/clk pin. the first time that the rt/clk is pulled above the pll threshold, the TPS54340B-Q1 device switches from the rt-resistor free-running frequency mode to the pll-synchronized mode. the internal 0.5-v voltage source is removed and the rt/clk pin becomes high impedance as the pll begins to lock onto the external signal. the switching frequency can be higher or lower than the frequency set with the rt/clk resistor. the device transitions from the resistor mode to the pll mode and locks onto the external clock frequency within 78 s. during the transition from the pll mode to the resistor-programmed mode, the switching frequency falls to 150 khz and then increases or decreases to the resistor programmed frequency when the 0.5-v bias voltage is reapplied to the rt/clk resistor. the switching frequency is divided by 8, 4, 2, and 1 as the fb pin voltage ramps from 0 to 0.8 v. the device implements a digital-frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. figure 26 , figure 27 and figure 28 show the device synchronized to an external system clock in continuous-conduction mode (ccm), discontinuous-conduction mode (dcm), and pulse-skip mode (eco-mode). spacer figure 25. synchronizing to a system clock ( ) ( ) f f ? ? + + ? = ? - + ? cl dc d out sc div sw(shift) on in cl d ds on i r v v t v i r v rt/clk TPS54340B-Q1 clock source pll rt rt/clk TPS54340B-Q1 hi-z clock source pll rt copyright ? 2016, texas instruments incorporated
18 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 26. plot of synchronizing in ccm figure 27. plot of synchronizing in dcm figure 28. plot of synchronizing in eco-mode ? 7.3.12 overvoltage protection the TPS54340B-Q1 device incorporates an output-overvoltage-protection (ovp) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low-output capacitance. for example, when the power-supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. if the fb pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current limit threshold. when the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. in some applications, the power-supply output voltage increases faster than the response of the error amplifier output resulting in an output overshoot. ext il sw ext il sw il ext sw
19 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) the ovp feature minimizes output overshoot when using a low-value output capacitor by comparing the fb-pin voltage to the rising ovp threshold which is nominally 109% of the internal voltage reference. if the fb-pin voltage is greater than the rising ovp threshold, the high-side mosfet is immediately disabled to minimize output overshoot. when the fb voltage drops below the falling ovp threshold, which is nominally 106% of the internal voltage reference, the high-side mosfet resumes normal operation. 7.3.13 thermal shutdown the TPS54340B-Q1 device provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176 c. the high-side mosfet stops switching when the junction temperature exceeds the thermal trip threshold. once the die temperature falls to less than 164 c, the device reinitiates the power-up sequence controlled by the internal soft-start circuitry. 7.3.14 small-signal model for loop response figure 29 shows an equivalent model for the TPS54340B-Q1 control loop, which is simulated to check the frequency response and dynamic load response. the error amplifier is a transconductance amplifier with a gm ea of 3350 a/v. the error amplifier is modeled using an ideal voltage-controlled current source. the resistor r o and capacitor c o model the open-loop gain and frequency response of the amplifier. the 1-mv ac-voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. plotting c/a provides the small-signal response of the frequency compensation. plotting a/b provides the small- signal response of the overall loop. the dynamic loop response is evaluated by replacing r l with a current source with the appropriate load-step amplitude and step rate in a time-domain analysis. this equivalent model is only valid for continuous conduction mode (ccm) operation. figure 29. small-signal model for loop response 7.3.15 simple small-signal model for peak-current-mode control figure 30 describes a simple small-signal model that is used to design the frequency compensation. the TPS54340B-Q1 power stage is approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. the control-to-output transfer function is shown in equation 11 and consists of a dc gain, one dominant pole, and one esr zero. the quotient of the change in switch current and the change in comp-pin voltage (node c in figure 29 ) is the power-stage transconductance, gm ps . the gm ps for the TPS54340B-Q1 device is 12 a/v. the low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in equation 12 . fb comp v o r1 r3 c1 c2 r2 co ro gm ea 350 m a/v 0.8 v power stage gm 12 a/v ps sw r esr c out r l b a c copyright ? 2016, texas instruments incorporated
20 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) as the load current increases and decreases, the low-frequency gain decreases and increases, respectively. this variation with the load is problematic at first glance, but fortunately the dominant pole moves with the load current (see equation 13 ). the combined effect is highlighted by the dashed line in the right half of figure 30 . as the load current decreases, the gain increases and the pole frequency lowers, which keeps the 0-db crossover frequency the same as load conditions vary. the type of output capacitor chosen determines whether the esr zero has a profound effect on the frequency compensation design. because the phase margin is increased by the esr zero of the output capacitor (see equation 14 ), the use of high-esr aluminum-electrolytic capacitors reduces the number frequency compensation components required to stabilize the overall loop. figure 30. simple small-signal model and frequency response for peak-current-mode control (11) (12) (13) (14) 7.3.16 small-signal model for frequency compensation the TPS54340B-Q1 device uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency-compensation circuits. the compensation circuits, type 2a, type 2b, and type 1, are shown in figure 31 . type 2 circuits are typically implemented in high-bandwidth power-supply designs using low -esr output capacitors. the type 1 circuit is used with power-supply designs with high-esr aluminum- electrolytic or tantalum capacitors. equation 15 and equation 16 relate the frequency response of the amplifier to the small-signal model in figure 31 . the open-loop gain and bandwidth are modeled using the r o and c o shown in figure 31 . see application and implementation for a design example using a type-2a network with a low-esr output capacitor. equation 15 through equation 24 are provided as a reference. an alternative is to use webench software tools to create a design based on the power supply requirements. z out esr 1 c r 2 = p f p out l 1 f c r 2 = p ps l adc = gm r z out c p s 1 2 v adc v s 1 2 ? ? + ? p ? = ? ? + ? p ? f f v o r esr c out r l vc gm ps fp fz adc
21 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 31. types of frequency compensation figure 32. frequency response of the type-2a and type-2b frequency compensation (15) (16) (17) (18) (19) (20) ea r2 a1 = gm ro| | r3 r1 + r2 ea r2 a0 = gm ro r1 + r2 f f f z1 p1 p2 s 1 2 ea a0 s s 1 1 2 2 ? ? + ? p ? = ? ? ? ? + + ? ? p p ? ? p ea o gm c = 2 bw (hz) ea aol(v/v) ro = gm a0a1 p1 z1 p2 aol bw vref v o r1 r3 c1 c2 r2 c o r o gm ea comp fb type 2a type 2b type 1 c2 r3 c1 copyright ? 2016, texas instruments incorporated 1 p1 2 ro c1 = p
22 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) (21) (22) (23) (24) 7.4 device functional modes the TPS54340B-Q1 device is designed to operate with input voltages above 4.5 v. when the vin voltage is above the 4.3 v, typical rising uvlo threshold and the en voltage is above the 1.2 v typical threshold the device is active. if the vin voltage falls below the typical 4-v uvlo turnoff threshold, the device stops switching. if the en voltage falls below the 1.2-v threshold, the device stops switching and enters a shutdown mode with low supply current of 2 a typical. the TPS54340B-Q1 device will operate in ccm when the output current is enough to keep the inductor current above 0 a at the end of each switching period. as a nonsynchronous converter, it will enter dcm at low-output currents when the inductor current falls to 0 a before the end of a switching period. at very low-output current, the comp voltage will drop to the pulse-skipping threshold, and the device operates in a pulse-skipping eco- mode. in this mode, the high-side mosfet does not switch every switching period. this operating mode reduces power loss while regulating the output voltage. for more information on eco-mode see the pulse skip eco-mode ? section. p o o 1 p2 = type 1 2 r (c2 + c ) p o o 1 p2 = type 2b 2 r3 | | r c p o o 1 p2 = type 2a 2 r3 | | r (c2 + c ) 1 z1 2 r3 c1 = p
23 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TPS54340B-Q1 device is a 42-v, 3.5-a, step-down regulator with an integrated high-side mosfet. this device is typically used to convert a higher dc voltage to a lower dc voltage with a maximum available output current of 3.5 a. example applications are: 12 v and 24 v industrial, automotive, and communications power systems. use the following design procedure to select component values for the TPS54340B-Q1 device. this procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. calculations can be done with the excel spreadsheet ( slvc452 ) located on the product page. 8.2 typical applications 8.2.1 buck converter with 6-v to 42-v input and 3.3-v at 3.5-a output figure 33. 3.3-v output TPS54340B-Q1 design example 8.2.1.1 design requirements to start the design process, a few parameters must be known. these requirements are typically determined at the system level. table 1 shows the design parameters for this example. 6 v to 42 v 3.3 v, 3.5 a 1 boot 2 vin 3 en 4 rt/clk 5 fb 6 comp 7 gnd 8 sw 9 pwrpd u1 TPS54340B-Q1 (dda) c5 5600 pf r4 11.5 k c8 47 pf c4 0.1 f l1 5.6 h r6 10.2 k r5 31.6 k r3 162 k r1 365 k r2 86.6 k c1 2.2 f c2 2.2 f d1 b560c c6 100 f gnd fb gnd gnd gnd vin fb vout gnd copyright ? 2016, texas instruments incorporated
24 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical applications (continued) table 1. design parameters design parameter example value output voltage 3.3 v transient response 0.875-a to 2.625 a-load step v out = 4 % maximum output current 3.5 a input voltage 12 v nominal, 6 v to 42 v output voltage ripple 0.5% of v out start input voltage (rising vin) 5.75 v stop input voltage (falling vin) 4.5 v 8.2.1.2 detailed design procedure 8.2.1.2.1 selecting the switching frequency the first step is to choose a switching frequency for the regulator. typically, the designer uses the highest switching frequency possible, because this produces the smallest solution size. high switching frequency allows for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. the switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage, and the frequency-foldback protection. equation 9 and equation 10 calculate the upper limit of the switching frequency for the regulator. choose the lower value result from the two equations. switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit. the typical minimum on time, t onmin , is 135 ns for the TPS54340B-Q1. for this example, the output voltage is 3.3 v and the maximum input voltage is 42 v, which allows for a maximum switch frequency up to 712 khz to avoid pulse skipping from equation 9 . to ensure overcurrent runaway is not a concern during short circuits use equation 10 to determine the maximum switching frequency for frequency-foldback protection. with a maximum input voltage of 42 v, assuming a diode voltage of 0.7 v, inductor resistance of 21 m , switch resistance of 92 m , a current limit value of 4.7 a, and short circuit output voltage of 0.1 v, the maximum switching frequency is 1260 khz. for this design, a lower switching frequency of 600 khz is chosen to operate comfortably below the calculated maximums. to determine the timing resistance for a given switching frequency, use equation 7 or the curve in figure 6 . the switching frequency is set by resistor r 3 shown in figure 33 . for 600 khz operation, the closest standard value resistor is 162 k . (25) (26) (27) 8.2.1.2.2 output inductor selection (l o ) to calculate the minimum value of the output inductor, use equation 28 . k ind is a ratio that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer, however, the following guidelines can be used. 1.008 101756 rt (k ) = = 161 k 600 (khz) w w f w + + ? ? = = ? w + ? sw(shift) 8 4.7 a x 21 m 0.1 v 0.7 v 1260 khz 135 ns 42 v - 4.7 a x 92 m 0.7 v f w + + ? ? = = ? w + ? sw(max skip) 1 3.5 a x 21 m 3.3 v 0.7 v 712 khz 135ns 42 v - 3.5 a x 92 m 0.7 v
25 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated for designs using low-esr output capacitors such as ceramics, a value as high as k ind = 0.3 is desirable. when using higher esr output capacitors, k ind = 0.2 yields better results. because the inductor ripple current is part of the current-mode pwm-control system, the inductor ripple current must always be greater than 150 ma for stable pwm operation. in a wide input voltage regulator, the best choice is a relatively large inductor ripple current which provides sufficient ripple current with the input voltage at the minimum. for this design example, k ind = 0.3 and the minimum inductor value is calculated to be 4.8 h. the nearest standard value is 5.6 h. not exceeding the rms current and saturation current ratings of the inductor is important. the rms and peak inductor current are determined by equation 30 and equation 31 . for this design, the rms inductor current is 3.5 a and the peak inductor current is 3.95 a. the chosen inductor is a we 7443552560, which has a saturation current rating of 7.5 a and an rms current rating of 6.7 a. as the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. selecting higher ripple currents increases the output-voltage ripple of the regulator but allow for a lower inductance value. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults, or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. in transient conditions, the inductor current increases up to the switch current limit of the device. for this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54340B-Q1, which is nominally 5.5 a. (28) spacer (29) spacer (30) spacer (31) 8.2.1.2.3 output capacitor there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance must be selected based on the most stringent of these three criteria. the desired response to a large change in the load current is the first criteria. the output capacitor must supply the increased load current until the regulator responds to the load step. the regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. the regulator generally requires two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. the output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. equation 32 shows the minimum output capacitance necessary, where i out is the change in output current, ? sw is the regulators switching frequency and v out is the allowable change in the output voltage. for this example, the transient load response is specified as a 4% change in v out for a load step from 0.875 a to 2.625 a. therefore, i out is 2.625 a ? 0.875 a = 1.75 a and v out = 0.04 3.3 = 0.13 v. using these numbers gives a minimum capacitance of 44.9 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to be ignored. aluminum- electrolytic and tantalum capacitors have higher esr that must be included in load step calculations. ( ) = + = + = ripple out l peak i 0.905 a i i 3.5 a 3.95 a 2 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) f ? ? - ? ? ? = + = + = ? ? ? m ? ? ? 2 2 out out in max 2 2 out l rms o sw in max v v v 3.3 v 42 v - 3.3 v 1 1 i i 3.5 a 3.5 a 12 v l 12 42 v 5.6 h 600 khz ( ) ( ) f - = = = m out out in max ripple o sw in max v (v v ) 3.3 v x (42 v - 3.3 v) i 0.905 a v l 42 v x 5.6 h x 600 khz ( ) ( ) ( ) f - = = = m out in max out o min out ind sw in max v v v 42 v - 3.3 v 3.3 v l 4.8 h i k v 3.5 a x 0.3 42 v 600 khz
26 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high- to-low load current. the catch diode of the regulator does not sink current so energy stored in the inductor produces an output-voltage overshoot when the load current rapidly decreases. a typical load-step response is shown in figure 34 . the excess energy absorbed in the output capacitor increases the voltage on the capacitor. the capacitor must be sized to maintain the desired output voltage during these transient periods. equation 33 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where l o is the value of the inductor, i oh is the output current under heavy load, i ol is the output under light load, v f is the peak output voltage, and v i is the initial voltage. for this example, the worst-case load step is from 2.625 a to 0.875 a. the output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage, which makes v f = 1.04 3.3 = 3.432. v i is the initial capacitor voltage, which is the nominal output voltage of 3.3 v. using these numbers in equation 33 yields a minimum capacitance of 38.6 f. equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ? sw is the switching frequency, v oripple is the maximum allowable output voltage ripple, and i ripple is the inductor ripple current. equation 34 yields 11.4 f. equation 35 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 35 indicates the esr must be less than 18 m . the most stringent criteria for the output capacitor is 44.9 f required to maintain the output voltage within regulation tolerance during a load transient. capacitance deratings for aging, temperature, and dc bias increases this minimum value. for this example, 100- f ceramic capacitors with 5 m of esr is used. the derated capacitance is 70 f, which is well above the minimum required capacitance of 44.9 f. capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. some capacitor data sheets specify the root mean square (rms) value of the maximum ripple current. equation 36 calculates the rms ripple current that the output capacitor must support. for this example, equation 36 yields 261 ma. (32) (33) (34) (35) (36) 8.2.1.2.4 catch diode the TPS54340B-Q1 device requires an external catch diode between the sw pin and gnd. the selected diode must have a reverse voltage rating equal to or greater than v in(max) . the peak current rating of the diode must be greater than the maximum inductor current. schottky diodes are typically a good choice for the catch diode due to their low forward voltage. the lower the forward voltage of the diode, the higher the efficiency of the regulator. typically, diodes with higher voltage and current ratings have higher forward voltages. a diode with a minimum of 42-v reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340B-Q1 device. for the example design, the b560c-13-f schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. the typical forward voltage of the b560c-13-f is 0.70 v at 5 a. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) > = m = m - 2 2 2 2 oh ol out o 2 2 2 2 f i i - i 2.625 a - 0.875 a c l x 5.6 h x 38.6 f 3.432 v 3.3 v v - v f d > = = m d out out sw out 2 i 2 1.75 a c 44.9 f v 600 khz x 0.13 v ( ) ( ) ( ) ( ) f - = = = m out out in max cout(rms) o sw in max v v v 3.3 v 42 v - 3.3 v i 261 ma 12 v l 12 42 v 5.6 h 600 khz < = = w oripple esr ripple v 16.5 mv r 18 m i 0.905 a f > = = m ? ? ? ? ? ? ? ? out sw oripple ripple 1 1 1 1 c x 11.4 f 16.5 mv 8 8 x 600 khz v 0.905 a i
27 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the diode must also be selected with an appropriate power rating. the diode conducts the output current during the off-time of the internal power switch. the off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. the output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. at higher switching frequencies, the ac losses of the diode must be taken into account. the ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. equation 37 is used to calculate the total power dissipation, including conduction losses and ac losses of the diode. the b560c-13-f diode has a junction capacitance of 300 pf. using equation 37 , the total loss in the diode is 2.42 w. if the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. (37) 8.2.1.2.5 input capacitor the TPS54340B-Q1 device requires a high-quality ceramic-type x5r or x7r input-decoupling capacitor with at least 3 f of effective capacitance. some applications benefit from additional bulk capacitance. the effective capacitance includes any loss of capacitance due to dc-bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple-current rating greater than the maximum input current ripple of the TPS54340B-Q1 device. equation 38 calculates the input ripple current. the value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. selecting a dielectric material that is more stable overtemperature minimizes capacitance variations due to temperature. x5r and x7r ceramic dielectrics are generally selected for switching regulator capacitors, because they have a high capacitance-to-volume ratio and are fairly stable over temperature. the input capacitor must also be selected with consideration for the dc bias. the effective value of a capacitor decreases as the dc bias across a capacitor increases. for this example design, a ceramic capacitor with at least a 42-v voltage rating is required to support the maximum input voltage. common-standard ceramic-capacitor voltage ratings include 4 v, 6.3 v, 10 v, 16 v, 25 v, 50 v, or 100 v. for this example, two 2.2- f, 100-v capacitors in parallel are used. table 2 shows several choices of high voltage capacitors. the input capacitance value determines the input ripple voltage of the regulator. equation 39 calculates the input voltage ripple. using the design example values, i out = 3.5 a, c in = 4.4 f, ? sw = 600 khz, yields an input voltage ripple of 331 mv and a rms input ripple current of 1.74 a. (38) (39) f d = = = m out in in sw i 0.25 3.5 a 0.25 v 331 mv c 4.4 f 600 khz ( ) ( ) ( ) ( ) ( ) ( ) - = = = out in min out out ci rms in min in min v v 6 v - 3.3 v v 3.3 v i i x x 3.5 a 1.74 a v v 6 v 6 v ( ) ( ) ( ) ( ) ( ) f f f - + = + = + + = 2 out out in max j sw in d in max 2 v v i v d c v v d p v 2 42 v - 3.3 v 3.5 a x 0.7 v 300 pf x 600 khz x (42 v 0.7 v) 2.42 w 42 v 2
28 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 2. capacitor types vendor value ( f) eia size voltage (v) dialectric comments murata 1 to 2.2 1210 100 x7r grm32 series 1 to 4.7 50 1 1206 100 grm31 series 1 to 2.2 50 vishay 1 to 1.8 2220 50 vj x7r series 1 to 1.2 100 1 to 3.9 2225 50 1 to 1.8 100 tdk 1 to 2.2 1812 100 c series c4532 1.5 to 6.8 50 1 to 2.2 1210 100 c series c3225 1 to 3.3 50 avx 1 to 4.7 1210 50 x7r dielectric series 1 100 1 to 4.7 1812 50 1 to 2.2 100 8.2.1.2.6 bootstrap-capacitor selection a 0.1- f ceramic capacitor must be connected between the boot and sw pins for proper operation. ti recommends a ceramic capacitor with x5r or better grade dielectric. the capacitor should have a 10-v or higher voltage rating. 8.2.1.2.7 undervoltage lockout set point the undervoltage lockout (uvlo) is adjusted using an external voltage divider on the en pin of the TPS54340B-Q1 device. the uvlo has two thresholds, one for power up when the input voltage is rising, and one for power-down or brown-outs when the input voltage is falling. for the example design, the supply turns on and starts switching once the input voltage increases above 5.75 v (uvlo start). after the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 v (uvlo stop). programmable uvlo-threshold voltages are set using the resistor divider of r uvlo1 and r uvlo2 between vin and ground connected to the en pin. equation 4 and equation 5 calculate the necessary resistance values. for the example application, a 365 k between vin and en (r uvlo1 ) and a 86.6 k between en and ground (r uvlo2 ) are required to produce the 8-v and 6.25-v start and stop voltages. (40) (41) 8.2.1.2.8 output voltage and feedback resistors selection the voltage divider of r5 and r6 sets the output voltage. for the example design, 10.2 k was selected for r6. using equation 3 , r5 is calculated as 31.9 k . the nearest standard 1% resistor is 31.6 k . because of the input current of the fb pin, the current flowing through the feedback network must be greater than 1 a to maintain the output voltage accuracy. this requirement is satisfied if the value of r6 is less than 800 k . choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but can also introduce noise immunity problems. (42) ? ? = = w = w ? ? out hs ls v - 0.8 v 3.3 v - 0.8 v r r x 10.2 k x 31.9 k 0.8 v 0.8 v = = = w + m + w ena uvlo2 start ena 1 uvlo1 v 1.2 v r 87.8 k v - v 5.75 v - 1.2 v 1.2 a i 365 k r = = = w m start stop uvlo1 hys v - v 5.75 v - 4.5 v r 368 k i 3.4 a
29 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.1.2.9 minimum v in to ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the device must be above the value calculated with equation 43 . using the typical values for the r ds(on) , r dc , and v f in this application example, the minimum input voltage is 3.83 v. the boot-sw = 3 v curve in figure 1 was used for r ds(on) = 0.12 because the device will be operating with low drop out. when operating with low dropout, the boot-sw voltage is regulated at a lower voltage because the boot-sw capacitor is not refreshed every switching cycle. in the final application, the values of r ds(on) , r dc , and v f used in this equation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application. in this application example the calculated minimum input voltage is near the input voltage uvlo for the TPS54340B-Q1 so the device may turn off before going into drop out. (43) 8.2.1.2.10 compensation there are several methods to design compensation for dc-dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. because the slope compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the calculations. this method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10-times greater the modulator pole. to get started, the modulator pole, ? p(mod) , and the esr zero, ? z1 , must be calculated using equation 44 and equation 45 . for c out , use a derated value of 70 f. use equations equation 46 and equation 47 to estimate a starting point for the crossover frequency, ? co . for the example design, ? p(mod) is 2411 hz and ? z(mod) is 455 khz. equation 45 is the geometric mean of the modulator pole and the esr zero and equation 47 is the mean of modulator pole and the switching frequency. equation 46 yields 33.1 khz and equation 47 gives 26.9 khz. use the lower value of equation 46 or equation 47 for an initial crossover frequency. for this example, the target ? co is 26.9 khz. next, the compensation components are calculated. a resistor in series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (44) (45) (46) (47) to determine the compensation resistor, r4, use equation 48 . assume the power-stage transconductance, gmps, is 12 a/v. the output voltage, v o , reference voltage, v ref , and amplifier transconductance, gmea, are 5 v, 0.8 v, and 350 a/v, respectively. r4 is calculated as 11.6 k , and a standard value of 11.5 k is selected. use equation 49 to set the compensation zero to the modulator pole frequency. equation 49 yields 5740 pf for compensating capacitor c5. 5600 pf is used for this design. (48) (49) f f f = = = sw co p(mod) x 600 khz 2411 hz x 26.9 khz 2 2 f f f = = = co p(mod) x z(mod) 2411 hz x 455 khz 33.1 khz ( ) f = = = p p w m z mod esr out 1 1 455 khz 2 r c 2 5 m 70 f ( ) ( ) f = = = p p m out max p mod out out i 3.5 a 2411 hz 2 v c 2 3.3 v 70 f ( ) ( ) ( ) out f dc out in ds out f in v v r i v min r on i v 0.99 3.3v 0.5v 0.0206 3.5a v min 0.12 3.5a 0.5v 3.83v 0.99 + + = + - + + w = + w - = f = = = p p w p(mod) 1 1 c5 5740 pf 2 r4 x 2 11.5 k x 2411 hz f ? ? p ? ? ? ? p m ? ? = = = w ? ? ? ? m ? ? ? ? f co out out ref 2 c v 2 26.9 khz 70 3.3 v r4 x x 11.6 k gmps v x gmea 12 a / v 0.8 v x 350 a / v
30 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated a compensation pole is implemented if desired by adding capacitor c8 in parallel with the series combination of r4 and c5. use the larger value calculated from equation 50 and equation 51 for c8 to set the compensation pole. the selected value of c8 is 47 pf for this design example. (50) (51) 8.2.1.2.11 power dissipation estimate the following formulas estimate the power dissipation of the TPS54340B-Q1 device under continuous-conduction mode (ccm) operation. these equations should not be used if the device is operating in discontinuous- conduction mode (dcm). the power dissipation of the ic includes conduction loss (p cond ), switching loss (p sw ), gate drive loss (p gd ) and supply current (p q ). for example calculations of the design example with the 12-v typical input voltage, see equation 52 through equation 55 . (52) spacer (53) spacer (54) spacer where ? i out is the output current (a) ? r ds(on) is the on-resistance of the high-side mosfet ( ) ? v out is the output voltage (v) ? v in is the input voltage (v) ? ? sw is the switching frequency (hz) ? t rise is the sw pin voltage rise time and can be estimated by trise = v in 0.16 ns/v + 3 ns ? q g is the total gate charge of the internal mosfet ? i q is the operating nonswitching supply current (55) therefore, (56) for given t a , (57) for given t j(max) = 150 c where ? p tot is the total device power dissipation (w) ? t a is the ambient temperature ( c) ? t j is the junction temperature ( c) ? r th is the thermal resistance of the package ( c/w) ? t j(max) is maximum junction temperature ( c) ? t a(max) is maximum ambient temperature ( c) (58) f = = = sw in sw out rise p v i t 12 v 600 khz 3.5 a 4.9 ns 0.123 w ( ) ( ) ? ? = = w = ? ? 2 2 out cond out ds on in v 3.3 v p i r 3.5 a 92 m 0.31 w v 12 v f = = = p w p 1 1 c8 46.1 pf r4 x sw x 11.5 k x 600 khz x m w = = = w out esr c x r 70 f x 5 m c8 30.4 pf r4 11.5 k ( ) ( ) = - th tot a max j max t t r p = + j a th tot t t r p = + + + = + + + = tot cond sw gd q p p p p p 0.31 w 0.123 w 0.022 w 0.0018 w 0.457 w = = m = q in q p v i 12 v 146 a 0.0018 w f = = = gd in g sw p v q 12 v 3nc 600 khz 0.022 w
31 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated additional power losses occur in the regulator circuit due to the inductor ac and dc losses, the catch diode, and pcb trace resistance impacting the overall efficiency of the regulator. 8.2.1.2.12 discontinuous conduction mode and eco-mode ? boundary with an input voltage of 12 v, the power supply enters discontinuous-conduction mode when the output current is less than 342 ma. the power supply enters eco-mode when the output current is lower than 31.4 ma. the input current draw is 237 a with no load. 8.2.1.3 application curves figure 34. load transient figure 35. line transient (8 v to 40 v) figure 36. start-up with vin figure 37. start-up with en time = 2 ms/div 2 v/div 5 v/div 2 v/div c3: en c2: v out c3c2 c1 c1: v in time = 2 ms/div 2 v/div 5 v/div 2 v/div c1: v in c3: en c2: v out c2 c3 c1 time = 100 s/div m 100 mv/div c3: v ac coupled out 1 a/div c4: i out c4c3 time = 4 ms/div 20 mv/div 10 v/div v v offset out -3.3 v in
32 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 38. output ripple ccm figure 39. output ripple dcm figure 40. output ripple psm figure 41. input ripple ccm figure 42. input ripple dcm figure 43. low dropout operation time = 2 s/div m 1 a/div 10 v/div 200 mv/div c3: v ac coupled in c1: sw c4: i l c2c4 c1 time = 2 ms/div 200 ma/div 10 v/div 20 mv/div c1: sw c4: i l c2: v ac coupled out c2 c4 c1 time = 2 s/div m 1 a/div 10 v/div 20 mv/div c2: v ac coupled out c1: sw c4: i l c2c4 c1 time = 2 s/div m 500 ma/div 10 v/div 10 mv/div c2: v ac coupled out c1: sw c4: i l c2 c4 c1 time = 2 s/div m 500 ma/div 10 v/div 50 mv/div c3: v ac coupled in c1: sw c4: i l c3 c4 c1 time = 20 s/div m 200 ma/div 2 v/div 20 mv/div c3: v ac coupled out c1: sw c4: i l no loaden floating c3 c4 v = 5.5 v v = 5 v in out
33 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 44. efficiency vs load current figure 45. light-load efficiency figure 46. efficiency vs load current figure 47. light-load efficiency figure 48. overall loop-frequency response figure 49. regulation vs load current -60 -40 -20 0 20 60 10 100 frequency - hz gain - db 40 -180 -120 -60 0 60 120 180 10000 100000 1000000 phase - degree 1000 phase gain -1 -0.8 -0.6 0.4 -0.2 0 0.2 0.4 0.6 1 0 0.5 1.0 1.5 2.0 i - output current - a o output voltage deviation - % 2.5 3.0 0.8 3.5 0 10 20 30 40 50 60 70 80 100 0 0.5 1.0 1.5 2.0 i - output current - a o efficiency - % 2.5 3.0 90 3.5 4.0 6vin 12vin24vin 36vin42vin 0 10 20 30 40 50 60 70 80 100 0.001 0.01 i - output current - a o efficiency - % 0.1 90 1 6vin 12vin24vin 36vin42vin 0 10 20 30 40 50 60 70 80 100 0 0.5 1.0 1.5 2.0 i - output current - a o efficiency - % 2.5 3.0 90 3.5 6vin 12vin24vin 36vin42vin 0 10 20 30 40 50 60 70 80 100 0.001 0.01 i - output current - a o efficiency - % 0.1 90 1 6vin 12vin24vin 36vin42vin
34 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 50. regulation vs input voltage 8.2.2 inverting power supply the TPS54340B-Q1 device can be used to convert a positive input voltage to a negative output voltage. example applications are amplifiers requiring a negative power supply. for a more detailed example, see slva317 . figure 51. TPS54340B-Q1 inverting power supply from application note ( slva317 ) sw vin gnd boot fb comp TPS54340B-Q1 en rt/clk cpole czero rcomp rt co lo cboot cin r1 r2 cd vin vout + + gnd copyright ? 2016, texas instruments incorporated -0.3 0.2 -0.1 0 0.1 0.2 0.3 5 10 15 20 v - input voltage - v in output voltage deviation - % 25 30 35 40 45
35 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 split-rail power supply the TPS54340B-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. example applications are amplifiers requiring a split-rail positive and negative voltage power supply. for a more detailed example, see slva369 . figure 52. TPS54340B-Q1 split-rail power supply based on application note ( slva369 ) 9 power supply recommendations the device is designed to operate from an input voltage supply range from 4.5 v to 42v. this input supply must remain within this range. if the input supply is located more than a few inches from the TPS54340B-Q1 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 100 f is a typical choice. 10 layout 10.1 layout guidelines layout is a critical portion of good power supply design. there are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. see figure 53 for a pcb layout example. ? to reduce parasitic effects, the vin pin should be bypassed to ground with a low esr ceramic bypass capacitor with x5r or x7r dielectric. ? take care to minimize the loop area formed by the bypass capacitor connections, the vin pin, and the anode of the catch diode. the sw pin should be routed to the cathode of the catch diode and to the output inductor. because the sw connection is the switching node, the catch diode and output inductor should be located close to the sw pin, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. ? the gnd pin should be tied directly to the power pad under the ic and the powerpad ? . the powerpad should be connected to internal pcb ground planes using multiple vias directly under the ic. ? for operation at full rated load, the top side ground area must provide adequate heat dissipating area. ? the rt/clk pin is sensitive to noise so the rt resistor should be located as close as possible to the ic and routed with minimal lengths of trace. ? the additional external components can be placed approximately as shown. ? it may be possible to obtain acceptable performance with alternate pcb layouts; however, this layout has been shown to produce good results, and is meant as a guideline. sw vin gnd boot fb comp TPS54340B-Q1 en rt/clk cpole czero rcomp rt coneg lo cboot cin r1 r2 cd vin voneg + + gnd vopos copos + copyright ? 2016, texas instruments incorporated
36 TPS54340B-Q1 slvsdx5 ? february 2017 www.ti.com product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 layout example figure 53. pcb layout example 10.3 estimated circuit area boxing in the components in the design of figure 33 , the estimated pcb area is 1.025 in 2 (661 mm 2 ). this area does not include test points or connectors. if the area must be reduced, then this can be done by using a two sided assembly, and replacing the 0603 sized passives with a smaller-sized equivalent. bootvin en rt/clk sw gnd comp fb inputbypass capacitor uvloadjust resistors frequencyset resistor compensationnetwork resistordivider outputinductor output capacitor vout vin topside ground area catchdiode route boot capacitor trace on another layer to provide wide path for topside ground thermal via signal via
37 TPS54340B-Q1 www.ti.com slvsdx5 ? february 2017 product folder links: TPS54340B-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.2 documentation support 11.2.1 related documentation for related documentation see the following: ? creating gsm power supply from tps54260 , slva412 . ? creating a universal car charger for usb devices from the tps54240 and tps2511 , slva464 . ? create an inverting power supply from a step-down regulator , slva317 . ? create a split-rail power supply with a wide input voltage buck regulator , slva369 . 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks eco-mode, powerpad, e2e are trademarks of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 9-feb-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps54340bqddaq1 preview so powerpad dda 8 75 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 5434bq tps54340bqddarq1 preview so powerpad dda 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 5434bq (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 9-feb-2017 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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